1. Technical Field
Various embodiments of the present disclosure generally relate to a semiconductor memory apparatus, and more particularly, to a redundancy circuit of a semiconductor memory apparatus.
2. Related Art
FIG. 1 is a diagram schematically illustrating a typical open bit line sense amplifier structure. In an open bit line sense amplifier structure of the semiconductor memory apparatus, respective sense amplifiers are shared by adjoining mats as shown in FIG. 1.
Briefly describing an operation of the open bit line sense amplifier structure, when data from a second mat MAT1 is outputted, a sense amplifier 3 is activated such that the voltage level of a bit line connected to the second mat MAT1 is amplified relative to a bit line connected to a third mat MAT2. Through such an operation, the semiconductor memory apparatus having the open bit line sense amplifier structure carries out the task of reading data from the second mat MAT1.
In the semiconductor memory apparatus having the open bit line sense amplifier structure, if any of the respective mats MAT0 through MAT3 fails to perform storing data, the failed mat, that is, the mat in which a memory cell failure occurs during a test is replaced with a redundant mat by a redundancy circuit.
The redundancy circuit of the open bit line sense amplifier structure is configured in such a manner that, for example, if a to memory cell failure occurs in one of the first mat MAT0 and the second mat MAT1, the failed mat is replaced with a redundant mat. In a similar manner, if a memory cell failure occurs in one of the third mat MAT2 and the fourth mat MAT3, the failed mat is replaced with a redundant mat.
Specifically, typical redundancy circuit of the open bit line sense amplifier structure is configured such that information of two adjoining mats is received through a single fuse and an address of the failed memory cell is set. If a real address inputted externally to the semiconductor memory apparatus corresponds to an address of the failed memory cell, a redundancy signal is enabled. If the redundancy signal is enabled, the failed mat is replaced with a redundant mat.
In the typical redundancy circuit of the open bit line sense amplifier structure, if a memory cell failure occurs in the third mat MAT2 connected to the sense amplifier 3, both a fuse for receiving the information of the first mat MAT0 and the second mat MAT1 and setting an address of the failed memory cell and a fuse for receiving the information of the third mat MAT2 and the fourth mat MAT3 and setting an address of the failed memory cell should be determined to be cut or not according to an address of the failed memory cell, thereby causing difficulties. This is because of the open bit line sense amplifier structure in which the sense amplifier 3 should amplify the data of the second mat MAT1 relative to a bit line connected to the third mat MAT2 which has a reference voltage level.
As a result, the typical redundancy circuit of the open bit line sense amplifier structure has a defect in that a number of fuses should be cut to replace the failed mat with a redundant mat, causing fuse utilization efficiency to deteriorate.